1. Field of the Invention
The present invention relates to complementary MOS logic circuits and, in particular, cascaded stages of dynamic complementary MOS circuits. In the present specification the abbreviation MOS is to mean both metal-oxide-semiconductor or MIS (metal-insulator-semiconductor) devices.
2. Description of the Prior Art
Because of its low power consumption and the stability of its output voltage, the complementary MOS (CMOS) logic circuit is particularly advantageous for use in present day electronic circuitry.
Typically CMOS logic circuits may be classified into two types, static and dynamic.
The first type, i.e. the static type of circuit, is described, for example, in the U.S. Pat. No. 3,356,858 to Wanlass, issued Dec. 5, 1967. An illustration of an exemplary circuit described therein is shown in FIG. 1 of the drawings of the present application, wherein P-type MOSFETs 10-12 and N-type MOSFETs 20-22 are depicted. The N-type MOSFETs 20-22 are connected in series, while the P-type MOSFETs 10-12 are connected in parallel. The gate electrodes of the N-type driver MOSFETs 10-12 are connected with the corresponding electrodes of the P-type MOSFETs 20-22, respectively. This static type of CMOS logic circuit requires a relatively large number of transistors, since a pair of MOSFETs, i.e. a P-type and an N-type MOSFET, are required for each input A, B, and C.
As an example of a dynamic type of logic circuit, reference may be had to the U.S. Pat. No. 3,551,693 to Burns et al, an example of the circuitry disclosed in which being shown in FIG. 2 of the drawings of the present application. In FIG. 2, a P-type MOSFET 10 and N-type MOSFETs 20-22 and 30 are depicted. The series connected N-type MOSFETs 20-22 make up a logic block (LB) shown in broken lines and are connected between the drain electrode of the P-type MOSFET 10 and the drain electrode of the N-type MOSFET 30. The gate electrode of the P-type MOSFET 10 is connected with the gate electrode of the N-type MOSFET 30 and a pulse signal .phi. is supplied to the commonly connected gate electrodes. The output from the circuit is taken from the common connection between the P-type MOSFET 10 and the N-type MOSFET 20.
A comparison of the dynamic type of circuit shown in FIG. 2 with the static type of circuit shown in FIG. 1, discussed above, will reveal that the number of transistors employed in the dynamic type of circuit can be reduced, since the number of load MOSFETs is decreased. As a result, the dynamic type of MOSFET can be more readily integrated into a semiconductor substrate.
However, this type of dynamic circuit is not without its own problems. Namely, when the circuit shown in FIG. 2 is connected in a cascade arrangement, the possibility of the circuit operating incorrectly exists. For a better understanding of this problem, attention is directed to FIGS. 3 and 4 of the drawings. FIG. 3 illustrates a cascade connection of the circuit shown in FIG. 2 and FIG. 4 illustrates voltage waveforms which exist at various portions of the circuit.
In FIG. 3, for purposes of simplification, the logic block LB of FIG. 2 is represented by a single MOSFET 20a or 20b, and the first and second gate stages are driven by the same pulse signal .phi..
In addition to the standard load capacitors CL.sub.1 and CL.sub.2 shown connected at the output of each respective gate stage, there are additional capacitors C.sub.1 and C.sub.2, the capacitors including both junction capacitances, gate capacitances and wiring capacitances. Furthermore, when the MOSFETs are turned on, they have channel resistances of several hundred ohms.
Now, with attention directed to FIG. 4, when a pulse signal .phi. which varies between the power supply voltage of +V.sub.DD and 0 volts, is switched from the high voltage (+V.sub.DD) to 0 volts, the P-type MOSFET 10a will be turned on, while the N-type MOSFET 30a will be turned off. As a result, capacitor CL.sub.1 is charged at a voltage +V.sub.DD through the MOSFET 10a. The period of time t.sub.1 as shown in FIG. 4 will be referred to as the "percharge period". The percharge period t.sub.1 should be so selected as to assure that the capacitor CL.sub.1 will be sufficiently charged so that a voltage of +V.sub.DD will be maintained thereacross, when considering the time constant determined by the capacitor CL.sub.1 and the channel resistance of MOSFET 10a.
Now, when the pulse signal .phi. switches back to the high potential (+V.sub.DD) the P-type MOSFET 10a will be turned off, while the N-type MOSFET 30a will be turned on. During this condition, if a voltage of +V.sub.DD is applied to the INPUT terminal, then MOSFET 20a will be turned on and the charge which has been stored in capacitor CL.sub.1 will be discharged through the series connection of MOSFETs 20a and 30a to ground. During this charging operation, the potential at the point X (the output of the first gate stage) will decrease exponentionally to a level of 0 volts (ground potential) from its high voltage level of +V.sub.DD, as shown by the curve portion a in FIG. 4, the time constant of the exponential decrease of the potential at point X being determined by the capacitor CL.sub.1 and the channel resistance of MOSFETs 20a and 30a.
With the gates of MOSFETs 10b and 30b also being supplied with a pulse signal .phi., then, when the pulse signal .phi. is at a level of 0 volts, as shown in FIG. 4, P-type MOSFET 10b will be turned on, while N-type MOSFET 30b will be turned off, so that the second load capacitor CL.sub.2 will be charged at a voltage of +V.sub.DD through MOSFET 10b.
When the pulse signal .phi. changes to the high level (+V.sub.DD) P-type MOSFET 10a will be turned off, while N-type MOSFET 30a will be turned on. During the period of time immediately after MOSFET 10b is turned off, the voltage at the point Y at the output of the second gate stage should be at the high level (+V.sub.DD), since MOSFETs 20a and 30a are turned on during this period.
However, since the voltage at the point X decreases exponentionally to a level of zero volts (ground potential), as discussed above, from its initial high level of +V.sub.DD, MOSFET 20b will remain turned on until the voltage level at the point X becomes lower than the threshold voltage of MOSFET 20b.
As a result, the charge stored in capacitor CL.sub.2 partially discharges through MOSFETS 20b and 30b to ground, so that the voltage level at the point Y does not remain at the high level of +V.sub.DD as intended, but drops to a lower voltage level, as shown by curve b in FIG. 4.
Because the voltage level b is lower than the threshold voltage of a MOSFET in the next subsequent cascaded stage connected to the output terminal Y, such a MOSFET will not be turned off, so that the operation of the circuit is defective.